1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory and, more particularly, to improvement in its integration.
2. Description of the Prior Art
There is shown an instance of semiconductor nonvolatile memory which utilize the ferroelectric properties: reversible polarization and remanance. This ferroelectric nonvolatile memory comprises many switch elements 1. FIG. 1 shows the switch element 1 in section.
Referring to FIG. 1, the switch element 1 has a P type silicon substrate 10 including a N.sup.+ type source 8 and a N.sup.+ type drain 6, the two regions forming a channel region 9. On top of the channel region 9 there is formed a ferroelectric film 4. Further, on top of the ferroelectric film 4 there is formed a gate electrode 2 comprised of aluminum or the like.
A logic "1" can be written into and erased from the above-mentioned switch elements 1 by electricity. Accordingly, the switch elements 1 have two stable states: one in which a logic "1" has been written therein, and the other in which the logic "1" has been erased and a logic "0" has been stored. The fact that the switch elements 1 can take these two stable states is utilized to fabricate a memory.
FIG. 2 shows hysteresis loop which the switch elements 1 exhibits. Referring to FIG. 2, the vertical axis represents polarization P and horizontal axis represents electric field E. There will be described the process by which the logic "1" is written into and erased from the switch element 1 with reference to FIG. 2.
In order to write a logic "1" into switch elements 1, ground potential is applied to the substrate 10 and more programming voltage than positive coercive voltage Ec is applied to the control electrode 2. Incidently, the coercive voltage Ec is the lowest positive possible voltage applied to the control electrode 2 so as to reverse the existing polarization. At that time, an electric field develops between the substrate 10 and the control electrode 2 whereby the ferroelectric film 4 is polarized into a direction parallel to the electric field, as symbolized by point P1 in FIG. 2. In addition, this polarization will remain in this state even if the gate voltage is cut off, as symbolized by point Q1 in FIG. 2.
This status in polarization of the ferroelectric film 4 indicates that a logic "1" has been written into the switch element 1. In the switch element 1 having the logic "1", the channel region 9 is conductive because a portion of the ferroelectric film near the control electrode 2 is negatively charged and a portion of the ferroelectric film 4 near the substrate 10 is positively charged.
On the other hand, in order to erase the logic "1" from the switch element 1 or to write a logic "0" therein, ground potential is applied to the substrate 10 and less programming voltage than negative coercive voltage -Ec is applied to the control electrode 2.
At that time, an electric field of the polarity opposite to that used when writing the logic "1" between the substrate 10 and the control electrode 2 is applied, whereby the ferroelectric film 4 is polarized into the direction parallel to the electric field, as symbolized by point R1 in FIG. 2. In addition, this polarization will remain in this state even if the gate voltage is cut off, as symbolized by point S1 in FIG. 2.
This status in polarization of the ferroelectric film 4 indicates that the logic "1" has been erased or a logic "0" has been written into the switch element 1. In the switch element 1 with the logic "0", the channel region 9 is nonconductive because a portion of the ferroelectric film 4 near the control electrode 2 is positively charged and a portion of the ferroelectric film near the substrate is negatively charged.
The operation of reading information from the switch element 1 will be described below. It is determined whether the switch element 1 has a logic "0" or a logic "1", by determining whether or not a current flows through the channel region 9 when stable voltage is applied between the source 8 and the drain 6 of the switch element 1.
An example of a memory circuit constructed using the aforementioned switch elements 1 is conceptually shown in FIG. 3.
A memory cell array A has 32 by 32, i.e. 1024 memory cells (1K bits) arranged in matrix form. To the drain 6 of each switch element 1 is connected the source of row select transistor 7. A row decoder 40 drives word lines WL which are each connected to the control electrodes of the switch elements 1. Select control lines SL are each connected to the gate electrodes of the row select transistors 7 to assist in writing and erasing data to the array. A column decoder 38 drives column data lines DLs which are each connected to the drain of each row select transistor 7.
The way in which information is written into a switch element 1 will be described with reference to FIG. 3. To write a logic "1" into a switch element 1.sub.m,n at column m and row n, programming voltage V.sub.pp grater than positive coercive voltage is applied only to the control electrode 2 of the switch element 1.sub.m,n relative the drain 6 thereof. This is effected by applying the programming voltage V.sub.pp to only the word line WLn with the low decoder 40, applying a voltage V.sub.dd to only the Select control line SLn, applying ground voltage equal in potential to the substrate 10 to the data line DLm and applying a programming inhibit voltage Vi to all data lines except the data line DLm. This potential difference V.sub.pp polarizes the ferroelectric film 4 of the switch element 1.sub.m,n into a direction parallel to the electric field developed thereby.
As is described above, the logic "1" will be written into only the switch element 1.sub.m,n.
The way in which the logic "1" stored in the switch element 1.sub.m,n is erased and changed into a logic "0" will be described with reference to FIG. 4. The construction shown in FIG. 4 is the same as shown in FIG. 3. To erase the logic "1" stored in the switch element 1.sub.m,n, an electric field of opposite polarity to that produced when writing the logic "1" is required between its control electrode 2 and its drain 6. This is effected by applying the voltage V.sub.pp to only the data line DLm with the column decoder 38, applying the voltage V.sub.dd to only the Select control line SLn and applying ground voltage equal in potential to the substrate 10.
This potential difference V.sub.pp polarizes the ferroelectric film 4 of the switch element 1.sub.m,n into a direction parallel to the electric field developed thereby. As is described above, the logic "1" will be erased from only the switch element 1.sub.m,n.
The method of operation for reading information from the switch element 1.sub.m,n will be described below with reference to FIG. 5. The construction shown in FIG. 5 is the same as shown in FIG. 3. In order to read data stored in the switch element 1.sub.m,n, it is necessary to determine which logic is stored in the switch element 1.sub.m,n and output the result.
More specifically, in reading operation, the voltage V.sub.dd is applied to only the line SLn among Select control lines SL and the data line DLm has the voltage V.sub.dd applied to it through a resistor 43. The source 8 of the switch element 1.sub.m,n is grounded. As a result, there is a potential difference V.sub.dd between the source 8 and the drain 6 because the row select transistors 7.sub.m,n, which are connected with the Select control line SLn, have a conductive channel formed between the source and the drain. The current flowing through data line DL.sub.m is directed to ground via the conductive switch element 1.sub.m,n on condition that the switch element has the logic "1" stored. This occurs because the channel region 9 of the switch element 1.sub.m,n is conductive. As a result, the column decoder 38 has no input of current from the data line DL.
Conversely, the current flowing through data line DLm is not conducted to ground through the switch element 1.sub.m,n and is therefore inputted into the column decoder 38 without loss to ground on condition that the switch element has the logic "0" stored. This occurs because the channel region of the switch element is nonconductive.
The column decoder 38 is arranged to output only the current from the data line DL.sub.m. This output is amplified and read by the sense amplifier 42. In the FIG. 5, the voltage V.sub.dd is applied the rest of data lines through the resistor 43 for the case where data are read from the other switch elements 1 at same time.
With progress of the semiconductor industry, a need has arisen for nonvolatile semiconductor memories which can be miniaturized and integrated. In response to this need, construction of a memory circuit has been attempted using only the aforementioned switch elements 1 without the row select transistors 7.
However, this memory circuit comprising one-transistor cells have the following problems. A conceptual view of the memory circuit comprising one-transistor cells is shown in FIG. 6. FIG. 6 shows four switch elements 1A, 1B, 1C and 1D arrayed in row by column. Drains of switch elements 1 arrayed in a row are each connected to a drain line and sources of switch elements 1 arrayed in a column are connected to a data line. Also, control electrodes of switch elements 1 arrayed in a column are each connected to a word line.
In order to read the information from the switch element 1A of the memory circuit, it is necessary to make the current flowing on only the data line 12, apply ground potential to only the drain line 20 and apply the same potential as the data line 12 to the rest of drain lines except the drain line 20, after setting all word lines to ground potential. It is determined whether the switch element 1 has a logic "0" or a logic "1", by determining whether or not there is decrease in potential of the word line 12 when the above-mentioned reading operation is performed. More Specifically, when the switch element 1 has the logic "1" stored, there is decrease in potential of the word line 12. Conversely, when the switch element 1 have the logic "0" stored, there is not decrease in potential of the word line 12.
However, when the switch element 1A has the logic "0" and the switch elements 1B, 1C and 1D have the logic "1" (that is, the switch element 1A is nonconductive and the switch elements 1B, 1C and 1D are conductive), there is a decrease in potential of the word line 12 in spite of the fact that the switch element 1A is nonconductive. This is because the current flowing through the data line 12 is directed to ground via the line symbolized as the thick exiting line. Such a misreading is possible in the memory circuit comprising the one-switch element 1.
For the above reason, the memory circuit comprising the one-switch element 1 has not been implemented.